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The capacitor in the stacked capacitor scheme is constructed above the surface of the substrate. The capacitor is constructed from an oxide-nitride-oxide ONO dielectric sandwiched in between two layers of polysilicon plates the top plate is shared by all DRAM cells in an IC , and its shape can be a rectangle, a cylinder, or some other more complex shape.
There are two basic variations of the stacked capacitor, based on its location relative to the bitline—capacitor-over-bitline COB and capacitor-under-bitline CUB. In a former variation, the capacitor is underneath the bitline, which is usually made of metal, and the bitline has a polysilicon contact that extends downwards to connect it to the access transistor's source terminal.
In the latter variation, the capacitor is constructed above the bitline, which is almost always made of polysilicon, but is otherwise identical to the COB variation.
The advantage the COB variant possesses is the ease of fabricating the contact between the bitline and the access transistor's source as it is physically close to the substrate surface. However, this requires the active area to be laid out at a degree angle when viewed from above, which makes it difficult to ensure that the capacitor contact does not touch the bitline.
RAS 2019: Books for Preliminary Exam
CUB cells avoid this, but suffer from difficulties in inserting contacts in between bitlines, since the size of features this close to the surface are at or near the minimum feature size of the process technology Kenner, pp. The trench capacitor is constructed by etching a deep hole into the silicon substrate.
A layer of oxide-nitride-oxide dielectric is grown or deposited, and finally the hole is filled by depositing doped polysilicon, which forms the top plate of the capacitor. The top of the capacitor is connected to the access transistor's drain terminal via a polysilicon strap Kenner, pp. Trench capacitors have numerous advantages. Since the capacitor is buried in the bulk of the substrate instead of lying on its surface, the area it occupies can be minimized to what is required to connect it to the access transistor's drain terminal without decreasing the capacitor's size, and thus capacitance Jacob, pp.
Alternatively, the capacitance can be increased by etching a deeper hole without any increase to surface area Kenner, pg. Another advantage of the trench capacitor is that its structure is under the layers of metal interconnect, allowing them to be more easily made planar, which enables it to be integrated in a logic-optimized process technology, which have many levels of interconnect above the substrate.
The fact that the capacitor is under the logic means that it is constructed before the transistors are.
This allows high-temperature processes to fabricate the capacitors, which would otherwise be degrading the logic transistors and their performance. Disadvantages of trench capacitors are difficulties in reliably constructing the capacitor's structures within deep holes and in connecting the capacitor to the access transistor's drain terminal Kenner, pg.
By the second-generation, the requirement to increase density by fitting more bits in a given area, or the requirement to reduce cost by fitting the same amount of bits in a smaller area, lead to the almost universal adoption of the 1T1C DRAM cell, although a couple of devices with 4 and 16 Kbit capacities continued to use the 3T1C cell for performance reasons Kenner, p. These performance advantages included, most significantly, the ability to read the state stored by the capacitor without discharging it, avoiding the need to write back what was read out non-destructive read.
A second performance advantage relates to the 3T1C cell has separate transistors for reading and writing; the memory controller can exploit this feature to perform atomic read-modify-writes, where a value is read, modified, and then written back as a single, indivisible operation Jacob, p.
Proposed cell designs[ edit ] The one-transistor, zero-capacitor 1T DRAM cell has been a topic of research since the lates. In 1T DRAM cells, the bit of data is still stored in a capacitive region controlled by a transistor, but this capacitance is no longer provided by a separate capacitor.
Considered a nuisance in logic design, this floating body effect can be used for data storage. This gives 1T DRAM cells the greatest density as well as allowing easier integration with high-performance logic circuits, since they are constructed with the same silicon on insulator process technologies.Atomic and Nucleus physics handwritten notes available in hindi language.
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